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Supercomputer architecture

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Approaches to supercomputer architecture have taken dramatic turns since the earliest systems were introduced in the 1960s. Early <a href="Supercomputer" title="Supercomputer">supercomputer</a> architectures pioneered by <a href="Seymour_Cray" title="Seymour Cray">Seymour Cray</a> relied on compact innovative designs and local <a href="Parallel_computing" title="Parallel computing">parallelism</a> to achieve superior computational peak performance.<a href="#cite_note-chen-1">[1]</a> However, in time the demand for increased computational power ushered in the age of <a href="Massively_parallel" title="Massively parallel">massively parallel</a> systems.

While the supercomputers of the 1970s used only a few <a href="Central_processing_unit" title="Central processing unit">processors</a>, in the 1990s, machines with thousands of processors began to appear and by the end of the 20th century, massively parallel supercomputers with tens of thousands of <a href="Commercial_off-the-shelf" title="Commercial off-the-shelf">commercial off-the-shelf</a> processors were the norm. Supercomputers of the 21st century can use over 100,000 processors (some being <a href="GPGPU" class="mw-redirect" title="GPGPU">graphic units</a>) connected by fast connections.<a href="#cite_note-Hoffman-2">[2]</a><a href="#cite_note-Jouppi-3">[3]</a>

Throughout the decades, the management of <a href="Heat_density" class="mw-redirect" title="Heat density">heat density</a> has remained a key issue for most centralized supercomputers.<a href="#cite_note-TH1-4">[4]</a><a href="#cite_note-Charley-5">[5]</a><a href="#cite_note-Rupak-6">[6]</a> The large amount of heat generated by a system may also have other effects, such as reducing the lifetime of other system components.<a href="#cite_note-Huang313-7">[7]</a> There have been diverse approaches to heat management, from pumping <a href="Fluorinert" title="Fluorinert">Fluorinert</a> through the system, to a hybrid liquid-air cooling system or air cooling with normal <a href="Air_conditioning" title="Air conditioning">air conditioning</a> temperatures.<a href="#cite_note-Tokhi-8">[8]</a><a href="#cite_note-sysx-9">[9]</a>

Systems with a massive number of processors generally take one of two paths: in one approach, e.g., in <a href="Grid_computing" title="Grid computing">grid computing</a> the processing power of a large number of computers in distributed, diverse administrative domains, is opportunistically used whenever a computer is available.<a href="#cite_note-Prodan-10">[10]</a> In another approach, a large number of processors are used in close proximity to each other, e.g., in a <a href="Computer_cluster" title="Computer cluster">computer cluster</a>. In such a centralized <a href="Massively_parallel" title="Massively parallel">massively parallel</a> system the speed and flexibility of the interconnect becomes very important, and modern supercomputers have used various approaches ranging from enhanced <a href="Infiniband" class="mw-redirect" title="Infiniband">Infiniband</a> systems to three-dimensional <a href="Torus_interconnect" title="Torus interconnect">torus interconnects</a>.<a href="#cite_note-Bluenight-11">[11]</a><a href="#cite_note-Torus-12">[12]</a>

<div class="mw-heading mw-heading2"><h2 id="Context_and_overview">Context and overview</h2></div>

Since the late 1960s the growth in the power and proliferation of supercomputers has been dramatic, and the underlying architectural directions of these systems have taken significant turns. While the early supercomputers relied on a small number of closely connected processors that accessed <a href="Shared_memory_architecture" class="mw-redirect" title="Shared memory architecture">shared memory</a>, the supercomputers of the 21st century use over 100,000 processors connected by fast networks.<a href="#cite_note-Hoffman-2">[2]</a><a href="#cite_note-Jouppi-3">[3]</a>

Throughout the decades, the management of <a href="Heat_density" class="mw-redirect" title="Heat density">heat density</a> has remained a key issue for most centralized supercomputers.<a href="#cite_note-TH1-4">[4]</a> <a href="Seymour_Cray" title="Seymour Cray">Seymour Cray</a>'s "get the heat out" motto was central to his design philosophy and has continued to be a key issue in supercomputer architectures, e.g., in large-scale experiments such as <a href="Blue_Waters" title="Blue Waters">Blue Waters</a>.<a href="#cite_note-TH1-4">[4]</a><a href="#cite_note-Charley-5">[5]</a><a href="#cite_note-Rupak-6">[6]</a> The large amount of heat generated by a system may also have other effects, such as reducing the lifetime of other system components.<a href="#cite_note-Huang313-7">[7]</a>

There have been diverse approaches to heat management, e.g., the <a href="Cray_2" class="mw-redirect" title="Cray 2">Cray 2</a> pumped <a href="Fluorinert" title="Fluorinert">Fluorinert</a> through the system, while <a href="System_X_(supercomputer)" title="System X (supercomputer)">System X</a> used a hybrid liquid-air cooling system and the <a href="Blue_Gene/P" class="mw-redirect" title="Blue Gene/P">Blue Gene/P</a> is air-cooled with normal <a href="Air_conditioning" title="Air conditioning">air conditioning</a> temperatures.<a href="#cite_note-Tokhi-8">[8]</a><a href="#cite_note-13">[13]</a><a href="#cite_note-theregister1-14">[14]</a> The heat from the <a href="Aquasar" title="Aquasar">Aquasar</a> supercomputer is used to warm a university campus.<a href="#cite_note-15">[15]</a><a href="#cite_note-16">[16]</a>

The heat density generated by a supercomputer has a direct dependence on the processor type used in the system, with more powerful processors typically generating more heat, given similar underlying <a href="Semiconductor_device" title="Semiconductor device">semiconductor technologies</a>.<a href="#cite_note-Huang313-7">[7]</a> While early supercomputers used a few fast, closely packed processors that took advantage of local parallelism (e.g., <a href="Instruction_pipelining" title="Instruction pipelining">pipelining</a> and <a href="Vector_processing" class="mw-redirect" title="Vector processing">vector processing</a>), in time the number of processors grew, and computing nodes could be placed further away, e.g., in a <a href="Computer_cluster" title="Computer cluster">computer cluster</a>, or could be geographically dispersed in <a href="Grid_computing" title="Grid computing">grid computing</a>.<a href="#cite_note-Hoffman-2">[2]</a><a href="#cite_note-Harry217-17">[17]</a> As the number of processors in a supercomputer grows, "<a href="Failure_rate" title="Failure rate">component failure rate</a>" begins to become a serious issue. If a supercomputer uses thousands of nodes, each of which may fail once per year on the average, then the system will experience several <a href="Component_failure" class="mw-redirect" title="Component failure">node failures</a> each day.<a href="#cite_note-sysx-9">[9]</a>

As the price/performance of <a href="GPGPU" class="mw-redirect" title="GPGPU">general purpose graphic processors</a> (GPGPUs) has improved, a number of <a href="Petaflop" class="mw-redirect" title="Petaflop">petaflop</a> supercomputers such as <a href="Tianhe-I" class="mw-redirect" title="Tianhe-I">Tianhe-I</a> and <a href="Nebulae_(computer)" title="Nebulae (computer)">Nebulae</a> have started to rely on them.<a href="#cite_note-GPGPU-18">[18]</a> However, other systems such as the <a href="K_computer" title="K computer">K computer</a> continue to use conventional processors such as <a href="SPARC" title="SPARC">SPARC</a>-based designs and the overall applicability of GPGPUs in general purpose high performance computing applications has been the subject of debate, in that while a GPGPU may be tuned to score well on specific benchmarks its overall applicability to everyday algorithms may be limited unless significant effort is spent to tune the application towards it.<a href="#cite_note-HansH-19">[19]</a> However, GPUs are gaining ground and in 2012 the <a href="Jaguar_supercomputer" class="mw-redirect" title="Jaguar supercomputer">Jaguar supercomputer</a> was transformed into <a href="Titan_(supercomputer)" title="Titan (supercomputer)">Titan</a> by replacing CPUs with GPUs.<a href="#cite_note-PC-20">[20]</a><a href="#cite_note-21">[21]</a><a href="#cite_note-TitanReg-22">[22]</a>

As the number of independent processors in a supercomputer increases, the way they access data in the <a href="File_system" title="File system">file system</a> and how they share and access <a href="Secondary_storage" class="mw-redirect" title="Secondary storage">secondary storage</a> resources becomes prominent. Over the years a number of systems for <a href="Distributed_file_system" class="mw-redirect" title="Distributed file system">distributed file management</a> were developed, e.g., the <a href="IBM_General_Parallel_File_System" class="mw-redirect" title="IBM General Parallel File System">IBM General Parallel File System</a>, <a href="BeeGFS" title="BeeGFS">BeeGFS</a>, the <a href="Parallel_Virtual_File_System" title="Parallel Virtual File System">Parallel Virtual File System</a>, <a href="Hadoop" class="mw-redirect" title="Hadoop">Hadoop</a>, etc.<a href="#cite_note-23">[23]</a><a href="#cite_note-24">[24]</a> A number of supercomputers on the <a href="TOP500" title="TOP500">TOP100</a> list such as the Tianhe-I use <a href="Linux" title="Linux">Linux</a>'s <a href="Lustre_(file_system)" title="Lustre (file system)">Lustre file system</a>.<a href="#cite_note-TH1-4">[4]</a>

<div class="mw-heading mw-heading2"><h2 id="Early_systems_with_a_few_processors">Early systems with a few processors</h2></div>

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</style><div role="note" class="hatnote navigation-not-searchable">See also: <a href="History_of_supercomputing" title="History of supercomputing">History of supercomputing</a></div>

The <a href="CDC_6600" title="CDC 6600">CDC 6600</a> series of computers were very early attempts at supercomputing and gained their advantage over the existing systems by relegating work to <a href="Peripheral_device" class="mw-redirect" title="Peripheral device">peripheral devices</a>, freeing the <a href="Central_processing_unit" title="Central processing unit">central processing unit</a> (CPU) to process actual data. With the Minnesota <a href="FORTRAN" class="mw-redirect" title="FORTRAN">FORTRAN</a> compiler the 6600 could sustain 500 kiloflops on standard mathematical operations.<a href="#cite_note-25">[25]</a>

Other early supercomputers such as the <a href="Cray_1" class="mw-redirect" title="Cray 1">Cray 1</a> and <a href="Cray_2" class="mw-redirect" title="Cray 2">Cray 2</a> that appeared afterwards used a small number of fast processors that worked in harmony and were uniformly connected to the largest amount of <a href="Shared_memory_architecture" class="mw-redirect" title="Shared memory architecture">shared memory</a> that could be managed at the time.<a href="#cite_note-Jouppi-3">[3]</a>

These early architectures introduced <a href="Parallel_computing" title="Parallel computing">parallel processing</a> at the processor level, with innovations such as <a href="Vector_processing" class="mw-redirect" title="Vector processing">vector processing</a>, in which the processor can perform several operations during one <a href="Clock_cycle" class="mw-redirect" title="Clock cycle">clock cycle</a>, rather than having to wait for successive cycles.

In time, as the number of processors increased, different architectural issues emerged.

Two issues that need to be addressed as the number of processors increases are the distribution of memory and processing. In the distributed memory approach, each processor is physically packaged close with some local memory. The memory associated with other processors is then "further away" based on <a href="Bandwidth_(computing)" title="Bandwidth (computing)">bandwidth</a> and <a href="Latency_(engineering)" title="Latency (engineering)">latency</a> parameters in <a href="Non-uniform_memory_access" title="Non-uniform memory access">non-uniform memory access</a>.

In the 1960s <a href="Instruction_pipelining" title="Instruction pipelining">pipelining</a> was viewed as an innovation, and by the 1970s the use of <a href="Vector_processor" title="Vector processor">vector processors</a> had been well established. By the 1980s, many supercomputers used parallel vector processors.<a href="#cite_note-Hoffman-2">[2]</a>

The relatively small number of processors in early systems, allowed them to easily use a <a href="Shared_memory_architecture" class="mw-redirect" title="Shared memory architecture">shared memory architecture</a>, which allows processors to access a common pool of memory. In the early days a common approach was the use of <a href="Uniform_memory_access" title="Uniform memory access">uniform memory access</a> (UMA), in which access time to a memory location was similar between processors. The use of <a href="Non-uniform_memory_access" title="Non-uniform memory access">non-uniform memory access</a> (NUMA) allowed a processor to access its own local memory faster than other memory locations, while <a href="Cache-only_memory_architecture" title="Cache-only memory architecture">cache-only memory architectures</a> (COMA) allowed for the local memory of each processor to be used as cache, thus requiring coordination as memory values changed.<a href="#cite_note-Hesham-26">[26]</a>

As the number of processors increases, efficient <a href="Inter-process_communication" title="Inter-process communication">interprocessor communication</a> and synchronization on a supercomputer becomes a challenge. A number of approaches may be used to achieve this goal. For instance, in the early 1980s, in the <a href="Cray_X-MP" title="Cray X-MP">Cray X-MP</a> system, <a href="Shared_register" title="Shared register">shared registers</a> were used. In this approach, all processors had access to <a href="Processor_register" title="Processor register">shared registers</a> that did not move data back and forth but were only used for interprocessor communication and synchronization. However, inherent challenges in managing a large amount of shared memory among many processors resulted in a move to more <a href="Distributed_computing" title="Distributed computing">distributed architectures</a>.<a href="#cite_note-Kowalik-27">[27]</a>

<div class="mw-heading mw-heading2"><h2 id="Massive_centralized_parallelism">Massive centralized parallelism</h2></div>

<div role="note" class="hatnote navigation-not-searchable">See also: <a href="Computer_cluster" title="Computer cluster">Computer cluster</a> and <a href="Massively_parallel_(computing)" class="mw-redirect" title="Massively parallel (computing)">Massively parallel (computing)</a></div>

During the 1980s, as the demand for computing power increased, the trend to a much larger number of processors began, ushering in the age of <a href="Massively_parallel" title="Massively parallel">massively parallel</a> systems, with <a href="Distributed_memory" title="Distributed memory">distributed memory</a> and <a href="Distributed_file_system" class="mw-redirect" title="Distributed file system">distributed file systems</a>,<a href="#cite_note-Hoffman-2">[2]</a> given that <a href="Shared_memory_architecture" class="mw-redirect" title="Shared memory architecture">shared memory architectures</a> could not scale to a large number of processors.<a href="#cite_note-Greg61-28">[28]</a> Hybrid approaches such as <a href="Distributed_shared_memory" title="Distributed shared memory">distributed shared memory</a> also appeared after the early systems.<a href="#cite_note-Jelica-29">[29]</a>

The computer clustering approach connects a number of readily available computing nodes (e.g. personal computers used as servers) via a fast, private <a href="Local_area_network" title="Local area network">local area network</a>.<a href="#cite_note-nbis-30">[30]</a> The activities of the computing nodes are orchestrated by "clustering middleware", a software layer that sits atop the nodes and allows the users to treat the cluster as by and large one cohesive computing unit, e.g. via a <a href="Single_system_image" title="Single system image">single system image</a> concept.<a href="#cite_note-nbis-30">[30]</a>

Computer clustering relies on a centralized management approach which makes the nodes available as orchestrated <a href="Server_(computing)" title="Server (computing)">shared servers</a>. It is distinct from other approaches such as <a href="Peer-to-peer" title="Peer-to-peer">peer-to-peer</a> or <a href="Grid_computing" title="Grid computing">grid computing</a> which also use many nodes, but with a far more <a href="Distributed_computing" title="Distributed computing">distributed nature</a>.<a href="#cite_note-nbis-30">[30]</a> By the 21st century, the <a href="TOP500" title="TOP500">TOP500</a> organization's semiannual list of the 500 fastest supercomputers often includes many clusters, e.g. the world's fastest in 2011, the <a href="K_computer" title="K computer">K computer</a> with a <a href="Distributed_memory" title="Distributed memory">distributed memory</a>, cluster architecture.<a href="#cite_note-31">[31]</a><a href="#cite_note-autogenerated371-32">[32]</a>

When a large number of local semi-independent computing nodes are used (e.g. in a cluster architecture) the speed and flexibility of the interconnect becomes very important. Modern supercomputers have taken different approaches to address this issue, e.g. <a href="Tianhe-1" title="Tianhe-1">Tianhe-1</a> uses a proprietary high-speed network based on the <a href="Infiniband" class="mw-redirect" title="Infiniband">Infiniband</a> QDR, enhanced with <a href="FeiTeng-1000" class="mw-redirect" title="FeiTeng-1000">FeiTeng-1000</a> CPUs.<a href="#cite_note-TH1-4">[4]</a> On the other hand, the <a href="Blue_Gene" class="mw-redirect" title="Blue Gene">Blue Gene</a>/L system uses a three-dimensional <a href="Torus" title="Torus">torus</a> interconnect with auxiliary networks for global communications.<a href="#cite_note-Bluenight-11">[11]</a> In this approach each node is connected to its six nearest neighbors. A similar torus was used by the <a href="Cray_T3E" title="Cray T3E">Cray T3E</a>.<a href="#cite_note-Torus-12">[12]</a>

Massive centralized systems at times use special-purpose processors designed for a specific application, and may use <a href="Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate arrays</a> (FPGA) chips to gain performance by sacrificing generality. Examples of special-purpose supercomputers include <a href="Belle_(chess_machine)" title="Belle (chess machine)">Belle</a>,<a href="#cite_note-Auto2G-9-33">[33]</a> <a href="IBM_Deep_Blue" class="mw-redirect" title="IBM Deep Blue">Deep Blue</a>,<a href="#cite_note-34">[34]</a> and <a href="Hydra_(chess)" title="Hydra (chess)">Hydra</a>,<a href="#cite_note-35">[35]</a> for playing <a href="Chess" title="Chess">chess</a>, <a href="Gravity_Pipe" title="Gravity Pipe">Gravity Pipe</a> for astrophysics,<a href="#cite_note-36">[36]</a> <a href="MDGRAPE-3" class="mw-redirect" title="MDGRAPE-3">MDGRAPE-3</a> for protein structure computation

molecular dynamics<a href="#cite_note-37">[37]</a> and <a href="Deep_Crack" class="mw-redirect" title="Deep Crack">Deep Crack</a>,<a href="#cite_note-38">[38]</a> for breaking the <a href="Data_Encryption_Standard" title="Data Encryption Standard">DES</a> <a href="Cipher" title="Cipher">cipher</a>.

<div class="mw-heading mw-heading2"><h2 id="Massive_distributed_parallelism">Massive distributed parallelism</h2></div>

<div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="Grid_computing" title="Grid computing">Grid computing</a> and <a href="Quasi-opportunistic_supercomputing" title="Quasi-opportunistic supercomputing">Quasi-opportunistic supercomputing</a></div>

<a href="Grid_computing" title="Grid computing">Grid computing</a> uses a large number of computers in distributed, diverse administrative domains. It is an opportunistic approach which uses resources whenever they are available.<a href="#cite_note-Prodan-10">[10]</a> An example is <a href="BOINC" class="mw-redirect" title="BOINC">BOINC</a> a <a href="Volunteer_computing" title="Volunteer computing">volunteer-based</a>, opportunistic grid system.<a href="#cite_note-vega-39">[39]</a> Some <a href="BOINC" class="mw-redirect" title="BOINC">BOINC</a> applications have reached multi-petaflop levels by using close to half a million computers connected on the internet, whenever volunteer resources become available.<a href="#cite_note-40">[40]</a> However, these types of results often do not appear in the <a href="TOP500" title="TOP500">TOP500</a> ratings because they do not run the general purpose <a href="Linpack" class="mw-redirect" title="Linpack">Linpack</a> benchmark.

Although grid computing has had success in parallel task execution, demanding supercomputer applications such as <a href="Numerical_weather_prediction" title="Numerical weather prediction">weather simulations</a> or <a href="Computational_fluid_dynamics" title="Computational fluid dynamics">computational fluid dynamics</a> have remained out of reach, partly due to the barriers in reliable sub-assignment of a large number of tasks as well as the reliable availability of resources at a given time.<a href="#cite_note-vega-39">[39]</a><a href="#cite_note-Gao-41">[41]</a><a href="#cite_note-mario-42">[42]</a>

In <a href="Quasi-opportunistic_supercomputing" title="Quasi-opportunistic supercomputing">quasi-opportunistic supercomputing</a> a large number of geographically <a href="Distributed_computing" title="Distributed computing">disperse computers</a> are orchestrated with <a href="Fault-tolerant_design" class="mw-redirect" title="Fault-tolerant design">built-in safeguards</a>.<a href="#cite_note-Kravtsov-43">[43]</a> The quasi-opportunistic approach goes beyond <a href="Volunteer_computing" title="Volunteer computing">volunteer computing</a> on a highly distributed systems such as <a href="BOINC" class="mw-redirect" title="BOINC">BOINC</a>, or general <a href="Grid_computing" title="Grid computing">grid computing</a> on a system such as Globus by allowing the <a href="Middleware" title="Middleware">middleware</a> to provide almost seamless access to many computing clusters so that existing programs in languages such as <a href="Fortran" title="Fortran">Fortran</a> or <a href="C_(programming_language)" title="C (programming language)">C</a> can be distributed among multiple computing resources.<a href="#cite_note-Kravtsov-43">[43]</a>

Quasi-opportunistic supercomputing aims to provide a higher quality of service than <a href="Grid_computing" title="Grid computing">opportunistic resource sharing</a>.<a href="#cite_note-44">[44]</a> The quasi-opportunistic approach enables the execution of demanding applications within computer grids by establishing grid-wise resource allocation agreements; and <a href="Fault-tolerant_system" class="mw-redirect" title="Fault-tolerant system">fault tolerant</a> message passing to abstractly shield against the failures of the underlying resources, thus maintaining some opportunism, while allowing a higher level of control.<a href="#cite_note-Prodan-10">[10]</a><a href="#cite_note-Kravtsov-43">[43]</a><a href="#cite_note-Iccs-45">[45]</a>

<div class="mw-heading mw-heading2"><h2 id="21st-century_architectural_trends">21st-century architectural trends</h2></div>

The air-cooled IBM <a href="Blue_Gene" class="mw-redirect" title="Blue Gene">Blue Gene</a> supercomputer architecture trades processor speed for low power consumption so that a larger number of processors can be used at room temperature, by using normal air-conditioning.<a href="#cite_note-theregister1-14">[14]</a><a href="#cite_note-46">[46]</a> The second-generation Blue Gene/P system has processors with integrated node-to-node communication logic.<a href="#cite_note-47">[47]</a> It is energy-efficient, achieving 371 <a href="FLOPS_per_watt" class="mw-redirect" title="FLOPS per watt">MFLOPS/W</a>.<a href="#cite_note-48">[48]</a>

The <a href="K_computer" title="K computer">K computer</a> is a <a href="Computer_cooling" title="Computer cooling">water-cooled</a>, homogeneous processor, <a href="Distributed_memory" title="Distributed memory">distributed memory</a> system with a <a href="Computer_cluster" title="Computer cluster">cluster architecture</a>.<a href="#cite_note-autogenerated371-32">[32]</a><a href="#cite_note-49">[49]</a> It uses more than 80,000 <a href="SPARC64_V#SPARC64_VIIIfx" title="SPARC64 V">SPARC64 VIIIfx</a> processors, each with eight <a href="Multi-core_processor" title="Multi-core processor">cores</a>, for a total of over 700,000 cores—almost twice as many as any other system. It comprises more than 800 cabinets, each with 96 computing nodes (each with 16 GB of memory), and 6 I/O nodes. Although it is more powerful than the next five systems on the TOP500 list combined, at 824.56 MFLOPS/W it has the lowest power to performance ratio of any current major supercomputer system.<a href="#cite_note-50">[50]</a><a href="#cite_note-aics-51">[51]</a> The follow-up system for the K computer, called the <a href="PRIMEHPC_FX10" title="PRIMEHPC FX10">PRIMEHPC FX10</a> uses the same six-dimensional torus interconnect, but still only one processor per node.<a href="#cite_note-postK-52">[52]</a>

Unlike the K computer, the <a href="Tianhe-1" title="Tianhe-1">Tianhe-1A</a> system uses a hybrid architecture and integrates CPUs and GPUs.<a href="#cite_note-TH1-4">[4]</a> It uses more than 14,000 <a href="Xeon" title="Xeon">Xeon</a> general-purpose processors and more than 7,000 <a href="Nvidia_Tesla" title="Nvidia Tesla">Nvidia Tesla</a> <a href="GPGPU" class="mw-redirect" title="GPGPU">general-purpose graphics processing units</a> (GPGPUs) on about 3,500 <a href="Blade_server" title="Blade server">blades</a>.<a href="#cite_note-53">[53]</a> It has 112 computer cabinets and 262 terabytes of distributed memory; 2 petabytes of disk storage is implemented via <a href="Lustre_(file_system)" title="Lustre (file system)">Lustre</a> clustered files.<a href="#cite_note-TheRegister-54">[54]</a><a href="#cite_note-Tianhe-1A-55">[55]</a><a href="#cite_note-56">[56]</a><a href="#cite_note-TH1-4">[4]</a> Tianhe-1 uses a proprietary high-speed communication network to connect the processors.<a href="#cite_note-TH1-4">[4]</a> The proprietary interconnect network was based on the <a href="Infiniband" class="mw-redirect" title="Infiniband">Infiniband</a> QDR, enhanced with Chinese-made <a href="FeiTeng-1000" class="mw-redirect" title="FeiTeng-1000">FeiTeng-1000</a> CPUs.<a href="#cite_note-TH1-4">[4]</a> In the case of the interconnect the system is twice as fast as the Infiniband, but slower than some interconnects on other supercomputers.<a href="#cite_note-cw-57">[57]</a>

The limits of specific approaches continue to be tested, as boundaries are reached through large-scale experiments, e.g., in 2011 IBM ended its participation in the <a href="Blue_Waters" title="Blue Waters">Blue Waters</a> petaflops project at the University of Illinois.<a href="#cite_note-regwater-58">[58]</a><a href="#cite_note-statesman-59">[59]</a> The Blue Waters architecture was based on the IBM <a href="POWER7" title="POWER7">POWER7</a> processor and intended to have 200,000 cores with a petabyte of "globally addressable memory" and 10 petabytes of disk space.<a href="#cite_note-Rupak-6">[6]</a> The goal of a sustained petaflop led to design choices that optimized single-core performance, and hence a lower number of cores. The lower number of cores was then expected to help performance on programs that did not scale well to a large number of processors.<a href="#cite_note-Rupak-6">[6]</a> The large globally addressable memory architecture aimed to solve memory address problems in an efficient manner, for the same type of programs.<a href="#cite_note-Rupak-6">[6]</a> Blue Waters had been expected to run at sustained speeds of at least one petaflop, and relied on the specific water-cooling approach to manage heat. In the first four years of operation, the National Science Foundation spent about $200 million on the project. IBM released the <a href="Power_775" class="mw-redirect" title="Power 775">Power 775</a> computing node derived from that project's technology soon thereafter, but effectively abandoned the Blue Waters approach.<a href="#cite_note-regwater-58">[58]</a><a href="#cite_note-statesman-59">[59]</a>

Architectural experiments are continuing in a number of directions, e.g. the <a href="Cyclops64" title="Cyclops64">Cyclops64</a> system uses a "supercomputer on a chip" approach, in a direction away from the use of massive distributed processors.<a href="#cite_note-60">[60]</a><a href="#cite_note-Guangming-61">[61]</a> Each 64-bit Cyclops64 chip contains 80 processors, and the entire system uses a <a href="Memory_address" title="Memory address">globally addressable</a> memory architecture.<a href="#cite_note-cyc64-62">[62]</a> The processors are connected with non-internally blocking crossbar switch and communicate with each other via global interleaved memory. There is no <a href="Data_cache" class="mw-redirect" title="Data cache">data cache</a> in the architecture, but half of each <a href="Static_random-access_memory" title="Static random-access memory">SRAM</a> bank can be used as a scratchpad memory.<a href="#cite_note-cyc64-62">[62]</a> Although this type of architecture allows unstructured parallelism in a dynamically non-contiguous memory system, it also produces challenges in the efficient mapping of parallel algorithms to a <a href="Multi-core_processor" title="Multi-core processor">many-core</a> system.<a href="#cite_note-Guangming-61">[61]</a>

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<div class="side-box-text plainlist">Wikimedia Commons has media related to <a href="https://commons.wikimedia.org/wiki/Category:Supercomputers" class="extiw external" title="commons:Category:Supercomputers">Supercomputers</a>.</div></div>

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<ul><li><a href="Supercomputer_operating_systems" class="mw-redirect" title="Supercomputer operating systems">Supercomputer operating systems</a></li>

<li><a href="Supercomputing_in_China" title="Supercomputing in China">Supercomputing in China</a></li>

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<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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<li id="cite_note-postK-52"><a href="#cite_ref-postK_52-0">^</a> Fujitsu Unveils Post-K Supercomputer<a rel="nofollow" class="external text" href="http://www.hpcwire.com/hpcwire/2011-11-07/fujitsu_unveils_post-k_supercomputer.html">HPC Wire Nov 7 2011</a>

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<li id="cite_note-statesman-59">^ <a href="#cite_ref-statesman_59-0">a</a> <a href="#cite_ref-statesman_59-1">b</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110806093332/http://www.statesman.com/business/ibms-unix-computer-business-is-booming-and-its-1701298.html">"The Statesman IBM's Unix computer business is booming"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.statesman.com/business/ibms-unix-computer-business-is-booming-and-its-1701298.html">the original</a> on 2011-08-06. Retrieved 2012-02-05.</cite>

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<li id="cite_note-Guangming-61">^ <a href="#cite_ref-Guangming_61-0">a</a> <a href="#cite_ref-Guangming_61-1">b</a> <cite id="CITEREFTanSreedhar,_Vugranam_C.Gao,_Guang_R.2009" class="citation journal cs1">Tan, Guangming; Sreedhar, Vugranam C.; Gao, Guang R. (13 November 2009). "Analysis and performance results of computing betweenness centrality on IBM Cyclops64". The Journal of Supercomputing. 56 (1): 1–24. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1007%2Fs11227-009-0339-9">10.1007/s11227-009-0339-9</a>. <a href="S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:10976819">10976819</a>.</cite>

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<li id="cite_note-cyc64-62">^ <a href="#cite_ref-cyc64_62-0">a</a> <a href="#cite_ref-cyc64_62-1">b</a> <cite id="CITEREFHai_JinDaniel_A._ReedWenbin_Jiang2005" class="citation book cs1">Hai Jin; Daniel A. Reed; Wenbin Jiang (2005). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=_kXVgF4_FlYC">Network and Parallel Computing: IFIP International Conference, NPC 2005, Beijing, China, November 30 - December 3, 2005; Proceedings</a>. Birkhäuser. pp. 132–133. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-3-540-29810-6</bdi>. Retrieved 15 June 2012.</cite>

</li>

</ol></div></div>

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</style><div id="Parallel_computing346" style="font-size:114%;margin:0 4em"><a href="Parallel_computing" title="Parallel computing">Parallel computing</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">General</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Distributed_computing" title="Distributed computing">Distributed computing</a></li>

<li><a href="Parallel_computing" title="Parallel computing">Parallel computing</a></li>

<li><a href="Parallel_algorithm" title="Parallel algorithm">Parallel algorithm</a></li>

<li><a href="Massively_parallel" title="Massively parallel">Massively parallel</a></li>

<li><a href="Cloud_computing" title="Cloud computing">Cloud computing</a></li>

<li><a href="High-performance_computing" title="High-performance computing">High-performance computing</a></li>

<li><a href="Multiprocessing" title="Multiprocessing">Multiprocessing</a></li>

<li><a href="Manycore_processor" title="Manycore processor">Manycore processor</a></li>

<li><a href="General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li>

<li><a href="Computer_network" title="Computer network">Computer network</a></li>

<li><a href="Systolic_array" title="Systolic array">Systolic array</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Levels</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li>

<li><a href="Task_parallelism" title="Task parallelism">Thread</a></li>

<li><a href="Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li>

<li><a href="Pipeline_(computing)" title="Pipeline (computing)">Pipeline</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Temporal_multithreading" title="Temporal multithreading">Temporal</a></li>

<li><a href="Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a> (SMT)</li>

<li><a href="Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li>

<li><a href="Speculative_multithreading" title="Speculative multithreading">Speculative</a> (SpMT)</li>

<li><a href="Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li>

<li><a href="Computer_multitasking#Cooperative_multitasking" title="Computer multitasking">Cooperative</a></li>

<li><a href="Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Clustered multi-thread</a> (CMT)</li>

<li><a href="Hardware_scout" title="Hardware scout">Hardware scout</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Theory</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Parallel_RAM" title="Parallel RAM">PRAM model</a></li>

<li><a href="Parallel_external_memory" title="Parallel external memory">PEM model</a></li>

<li><a href="Analysis_of_parallel_algorithms" title="Analysis of parallel algorithms">Analysis of parallel algorithms</a></li>

<li><a href="Amdahl's_law" title="Amdahl's law">Amdahl's law</a></li>

<li><a href="Gustafson's_law" title="Gustafson's law">Gustafson's law</a></li>

<li><a href="Cost_efficiency" title="Cost efficiency">Cost efficiency</a></li>

<li><a href="Karp%E2%80%93Flatt_metric" title="Karp–Flatt metric">Karp–Flatt metric</a></li>

<li><a href="Parallel_slowdown" title="Parallel slowdown">Slowdown</a></li>

<li><a href="Speedup" title="Speedup">Speedup</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Elements</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Process_(computing)" title="Process (computing)">Process</a></li>

<li><a href="Thread_(computing)" title="Thread (computing)">Thread</a></li>

<li><a href="Fiber_(computer_science)" title="Fiber (computer science)">Fiber</a></li>

<li><a href="Instruction_window" title="Instruction window">Instruction window</a></li>

<li><a href="Array_(data_structure)" title="Array (data structure)">Array</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Coordination</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Multiprocessing" title="Multiprocessing">Multiprocessing</a></li>

<li><a href="Memory_coherence" title="Memory coherence">Memory coherence</a></li>

<li><a href="Cache_coherence" title="Cache coherence">Cache coherence</a></li>

<li><a href="Cache_invalidation" title="Cache invalidation">Cache invalidation</a></li>

<li><a href="Barrier_(computer_science)" title="Barrier (computer science)">Barrier</a></li>

<li><a href="Synchronization_(computer_science)" title="Synchronization (computer science)">Synchronization</a></li>

<li><a href="Application_checkpointing" title="Application checkpointing">Application checkpointing</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_programming" title="Computer programming">Programming</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Stream_processing" title="Stream processing">Stream processing</a></li>

<li><a href="Dataflow_programming" title="Dataflow programming">Dataflow programming</a></li>

<li><a href="Parallel_programming_model" title="Parallel programming model">Models</a>

<ul><li><a href="Implicit_parallelism" title="Implicit parallelism">Implicit parallelism</a></li>

<li><a href="Explicit_parallelism" title="Explicit parallelism">Explicit parallelism</a></li>

<li><a href="Concurrency_(computer_science)" title="Concurrency (computer science)">Concurrency</a></li></ul></li>

<li><a href="Non-blocking_algorithm" title="Non-blocking algorithm">Non-blocking algorithm</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_hardware" title="Computer hardware">Hardware</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Flynn's_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a>

<ul><li><a href="Single_instruction%2C_multiple_threads" title="Single instruction, multiple threads">Array processing</a> (SIMT)</li>

<li><a href="Flynn's_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li>

<li><a href="Flynn's_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li></ul></li>

<li><a href="Dataflow_architecture" title="Dataflow architecture">Dataflow architecture</a></li>

<li><a href="Instruction_pipelining" title="Instruction pipelining">Pipelined processor</a></li>

<li><a href="Superscalar_processor" title="Superscalar processor">Superscalar processor</a></li>

<li><a href="Vector_processor" title="Vector processor">Vector processor</a></li>

<li><a href="Multiprocessing" title="Multiprocessing">Multiprocessor</a>

<ul><li><a href="Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric</a></li>

<li><a href="Asymmetric_multiprocessing" title="Asymmetric multiprocessing">asymmetric</a></li></ul></li>

<li><a href="Semiconductor_memory" title="Semiconductor memory">Memory</a>

<ul><li><a href="Shared_memory" title="Shared memory">shared</a></li>

<li><a href="Distributed_memory" title="Distributed memory">distributed</a></li>

<li><a href="Distributed_shared_memory" title="Distributed shared memory">distributed shared</a></li>

<li><a href="Massively_parallel" title="Massively parallel">Massively parallel</a> computer</li>

<li><a href="Computer_cluster" title="Computer cluster">Computer cluster</a>

<ul><li><a href="Beowulf_cluster" title="Beowulf cluster">Beowulf cluster</a></li></ul></li>

<li><a href="Grid_computing" title="Grid computing">Grid computer</a></li>

<li><a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="API" title="API">APIs</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Ateji_PX" title="Ateji PX">Ateji PX</a></li>

<li><a href="Boost_(C%2B%2B_libraries)" title="Boost (C++ libraries)">Boost</a></li>

<li><a href="Chapel_(programming_language)" title="Chapel (programming language)">Chapel</a></li>

<li><a href="Charm%2B%2B" title="Charm++">Charm++</a></li>

<li><a href="Coarray_Fortran" title="Coarray Fortran">Coarray Fortran</a></li>

<li><a href="Dryad_(programming)" title="Dryad (programming)">Dryad</a></li>

<li><a href="Global_Arrays" title="Global Arrays">Global Arrays</a></li>

<li><a href="GPUOpen" title="GPUOpen">GPUOpen</a></li>

<li><a href="OpenMP" title="OpenMP">OpenMP</a></li>

<li><a href="OpenCL" title="OpenCL">OpenCL</a></li>

<li><a href="OpenHMPP" title="OpenHMPP">OpenHMPP</a></li>

<li><a href="OpenACC" title="OpenACC">OpenACC</a></li>

<li><a href="Parallel_Extensions" title="Parallel Extensions">Parallel Extensions</a></li>

<li><a href="Pthreads" title="Pthreads">pthreads</a></li>

<li><a href="RaftLib" title="RaftLib">RaftLib</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Problems</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Automatic_parallelization" title="Automatic parallelization">Automatic parallelization</a></li>

<li><a href="Deadlock_(computer_science)" title="Deadlock (computer science)">Deadlock</a></li>

<li><a href="Deterministic_algorithm" title="Deterministic algorithm">Deterministic algorithm</a></li>

<li><a href="Embarrassingly_parallel" title="Embarrassingly parallel">Embarrassingly parallel</a></li>

<li><a href="Parallel_slowdown" title="Parallel slowdown">Parallel slowdown</a></li>

<li><a href="Race_condition" title="Race condition">Race condition</a></li>

<li><a href="Software_lockout" title="Software lockout">Software lockout</a></li>

<li><a href="Scalability" title="Scalability">Scalability</a></li>

<li><a href="Starvation_(computer_science)" title="Starvation (computer science)">Starvation</a></li></ul>

</div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>

<ul><li> Category: Parallel computing</li></ul>

</div></td></tr></tbody></table></div></div><div><div class="zim-footer">

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